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| preliminary 0.18 , six layer metal cmos process 1.8 v vcc, 1.8/2.5/3.3 v drive capable i/o up to 4,008 dedicated flip-flops up to 55.3 k embedded ram bits up to 313 i/o up to 370 k system gates ieee 1149.1 boundary scan testing compliant low power capability up to twenty-four 2,304 bit dual port high performance sram blocks up to 55,296 embedded ram bits ram/rom/fifo wizard for automatic configuration configurable and cascadable ! high performance i/o cell with tco< 3 ns programmable slew rate control programmable i/o standards: lvttl, lvcmos, lvcmos18, pci, gtl+, sstl2, and sstl3 independent i/o banks capable of supporting multiple standards in one device i/o register configurations: input, output, output enable (oe) "# $% &$ multiple dedicated low skew clock networks high drive input-only networks quadrant-based segmentable clock networks user programmable phase locked loops #' " (" )#( * hardwired dsp building blocks with integrated multiply, add, and accumulate functions. + the quicklogic products come with secure vialink ? technology that protects intellectual property from design theft and reverse engineering. no external configuration memory needed; instant-on at power-up. embedded ram blocks pll pll fabric embeded computational units embedded ram blocks pll pll &&, #"" - "." +." ' / + preliminary 0 1$2$ "- & the quickworks ? package provides the most complete esp and fpga software solution from design entry to logic synthesis, to place and route, and simulation. the package provides a solution for designers who use third party to ols from cadence, mentor, orcad, synopsys, viewlogic, and other third-party tools for design entry, synthesis, or simulation. eclipse-ii is fabricated on a 0.18 , six layer metal cmos process. the core voltage is 1.8 v vcc supply and the i/os are up to 3.3 v tole rant. the eclipse-ii product line is available in commercial, industrial, and mi litary temperature grades. 13405 13454 1354 13054 13605 max gates 47,052 63,840 188,946 248,160 320,640 logic array 16 x 8 16 x 16 32 x 20 40 x 24 48 x 32 logic cells 128 256 640 960 1,536 max flip-flops 526 884 1,697 2,670 4,002 max i/o 90 124 139 250 310 ram modules 4 4 16 20 24 ram bits 9,216 9,216 36,864 46,100 55,300 plls 0 0 0 4 4 ecus 0 0 0 10 12 packages vqfp 100 100 100 - - csbga (0.8 mm) 196 196 196 - - pqfp 208 208 208 208 208 fbga (0.8 mm) - - - 280 280 bga (1.0 mm) - - - 484 484 !"#$ ! % & & 4471 89#:, 0431 034#:, ;3;:, ql8025 62 90 90 - - ql8050 62 100 124 - - ql8150 62 100 139 - - ql8250 - - 115 163 250 ql8325 - - 115 163 310 preliminary 6 !& the eclipse-ii logic cell structure is presented in 0 . this architectural feature addresses today's register-intensive designs. the eclipse-ii logic cell structure presented in 0 is a dual register, multiplexor-based logic cell. it is designed for wide fan- in and multiple, simultaneous outp ut funtions. both registers share clk, set, and reset inputs. the second register has a two-to-one mult iplexer controlling its input. the register can be loaded from the nz output or directly from a dedicated input. note: '&& &(&(&' & & ' &'' ')*+ ,- && '. + / ' & & & & && & ' && the complete logic cell consists of two 6-input and gates, four two-input and gates, seven two- to-one multiplexers, and two d flip-flops with asynchronous set and reset controls. the cell has a fan-in of 30 (including register control lines) , fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and tw o registered). the high logic capacity and fan-in of the logic cell accommodates many us er functions with a single level of logic delay while other architectures requi re two or more levels of delay. 01 &, & " " ' " & ', ', multiplexer 16:1 5 ns 2.8 ns parity tree 24 6 ns 3.4 ns counter 36 6 ns 3.4 ns 16 bit 250 mhz 450 mhz 32 bit 250 mhz 450 mhz fifo 128 x 32 155 mhz 280 mhz 256 x 16 155 mhz 280 mhz 128 x 64 155 mhz 280 mhz clock-to-out 4.5 ns 2.5 ns system clock 200 mhz 400 mhz preliminary ; the eclipse-ii product family includes up to 24 dual-po rt 2,304-bit ram modules for implementing ram, rom, and fi fo functions. each module is user-configurable into four different block organizations and ca n be cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown in ; . !""# the number of ram modules varies from 4 to 24 blocks for a tota l of 9.2 k to 55.3 k bits of ram. using two "mode" pins, designers can c onfigure each module into 128 x 18 (mode 0), 256 x 9 (mode 1), 512 x 4 (mode 2), or 1024 x 2 bloc ks (mode 3). the blocks are also easily cascadable to increase their e ffective width and/or depth (see ; ). qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 ps pp mp az oz qz nz fz q2z qc qr mode[1:0] wa[9:0] wd[17:0] we wclk 2 , 30 4-bit ram module asyncrd ra[9:0] rd[17:0] re rclk preliminary 5 ## !""# the ram modules are dual-port, with complete ly independent read and write ports and separate read and write cloc ks. the read ports support as ynchronous and synchronous operation, while the write ports support synchr onous operation. each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchro nous write operation. the read enable (re) acts as a clock enable for synchr onous read operation (asyncrd input low), or as a flow-through enable for asynchronous read operat ion (asyncrd input high). designers can cascade multiple ram modules to in crease the depth or width allowed in single modules by connecting corresponding address li nes together and dividi ng the words between modules. a similar technique can be used to create depths greater than 512 words. in this case address signals higher than the ninth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multip lexed together using encoded higher read address bits for the mu ltiplexer select signals. the ram blocks can be loaded with data generated internally (typically for ram or fifo functions) or with data fr om an external prom (typ ically for rom functions). #' " (" )#(* traditional programmable logic ar chitectures do not implement arithmetic functions efficiently or effectively?these functions require high logic cell usage while garnering only moderate performance results. the eclipse-ii architecture allows for functiona lity above and beyond that achievable using programmable logic devices. by embedding a dyna mically reconfigurable computational unit, the eclipse-ii device can address various arithmetic func tions efficiently. this approach offers greater performance than traditional programmable logic implementations. the embedded block is implemented at the transistor level as shown in 5 . wdata rdata rdata waddr wdata raddr ram module (2,304 bits) ram module (2,304 bits) preliminary 9 $ % the eclipse-ii ecu blocks ( < ; ) are placed next to the sram circuitry for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. up to twelve 8-bit mac functions can be implem ented per cycle for a total of 1 billion macs/s when clocked at 100 mhz. additi onal multiply-accumul ate functions can be implemented in the programmable logic. 2%34 #( ql8325 12 ql8250 10 ql8150 0 ql8050 0 ql8025 0 a[0:15] b[0:15] sign2 sign1 cin s1 s2 s3 a b c d 3-4 decoder 8-bit multiplier 16-bit adder 17-bit register 2-1 mux 2-1 mux 3-1 mux q[16:0] clk reset dq 00 01 10 a[7:0] a[15:8] preliminary = the modes for the ecu block are dynamically re -programmable through the programmable logic. note: & & & < 5 &56 % % & & $')* "- " instead of requiring extra components, designer s simply need to instantiate one of the pre- configured models (described in this section). the quicklogic bui lt-in plls support a wider range of frequencies than many other plls. these plls al so have the ability to support different ranges of frequency multiplications or divisions, driving th e device at a faster or slower rate than the incoming clock frequency. when plls are cascaded, the clock si gnal must be routed off-chip through the pllpad_out pin prior to routing into another pll; in ternal routing cannot be used for cascading plls. plls achieve a very short clock-to-out time?general ly less than 3 ns. this low clock-to-out time is achieved by the pll subtract ing the clock tree delay through the feedback path, effectively making the clock tree delay zero. 7%3 ,% " " !' " #(-" . /= 2## a. t pd , t su and t co do not include routing path s in/out of the ecu block. 0 6 ( #! 0 0 0 multiply 6.6 ns max 0 0 1 multiply-add 8.8 ns max 0 1 0 accumulate b b. internal feedback path in ecu restricts max clk fr equency to 238 mhz. 3.9 ns min 1.2 ns max 0 1 1 add 3.1 ns max 1 0 0 multiply (registered) c c. b [15:0] set to zero. 9.6 ns min 1.2 ns max 1 0 1 multiply- add (registered) 9.6 ns min 1.2 ns max 1 1 0 multiply - accumulate 9.6 ns min 1.2 ns max 1 1 1 add (registered) 3.9 ns min 1.2 ns max preliminary 3 9 illustrates a quicklogic pll. & ' f in represents a very stable high-frequency input cl ock and produces an accu rate signal reference. this signal can either bypass the pll entirely, thus entering the clock tree di rectly, or it can pass through the pll itself. within the pll, a voltage-controlled oscillator (vco) is added to the circuit. the external f in signal and the local vco form a control loop. the vco is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in 9 ) can compare the two signals. if the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through th e charge pump and loop filter ( 9 ). the charge pump generates an error voltage to bring the vco back into alignment, and the loop filter removes any high frequency noise before the error voltage en ters the vco. this new vco signal enters the clock tree to drive the chip's circuitry. f out represents the clock signal emerging from th e output pad (the output signal pllpad_out is explained in < = ). this clock signal is meaningful only when the pll is configured for external use; otherwise, it remains in high z state. most quicklogic products contain four plls. the pll presented in 9 controls the clock tree in the fourth quadrant of its fpga. quic klogic plls compensate for the additional delay created by the clock tree itself, as previously noted, by subtractin g the clock tree delay through the feedback path. for more specific informatio n on the phase locked loops, please refer to quicklogic application note 58. -!' " quicklogic plls have eight modes of operation, based on the input frequency and desired output frequency? < 9 indicates the features of each mode. vco filter f in f out + - 1st quadrant 2nd quadrant 3rd quadrant 4th quadrant clock tree frequency divide frequency multiply 1 . _ . 2 . _ . 4 . _ . 4 . _ . 2 . _ . 1 . . _ pll bypass preliminary 8 note: (8 ( &1 (' '1& ( &(9 ( &1 ( 1& ( the input frequency can range fr om 16 mhz to 300 mhz, while ou tput frequency ranges from 25 mhz to 250 mhz. when you add plls to your top-level design , be sure that the pll mode matches your desired inpu t and output frequencies. " < = summarizes the key signal s in quicklogic's plls. note: 4 99%9:;* &99;<, & ' $99;*/#= &99/#;"3 ' "3 /#= & ' $ & & >99 & ! ' >"+ "' >"+ " ! ' >"+ " pll_hf same as input 66 mhz?150 mhz 66 mhz?150 mhz pll_lf same as input 25 mhz?133 mhz 25 mhz?133 mhz pll_mult2hf 2x 50 mhz?125 mhz 100 mhz?250 mhz pll_mult2lf 2x 16 mhz?50 mhz 32 mhz?100 mhz pll_div2hf 1/2x 100 mhz?250 mhz 50 mhz?125 mhz pll_div2lf 1/2x 50 mhz?100 mhz 25 mhz?50 mhz pll_mult4 4x 16 mhz?40 mhz 64 mhz?160 mhz pll_div4 1/4x 100 mhz?300 mhz 25 mhz?75 mhz 5.9 99, & " % ' " pllclk_in input clock signal pll_reset active high reset if pll_reset is asserted, then clknet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. onn_offchip pll output this signal selects whether the pll will drive the internal clock network or be used off-chip. this is a static signal, not a dynamic signal. tied to gnd = outgoing signal drives internal gates. tied to vcc = outgoing signal used off-chip. clknet_out out to internal gates this signal bypasses the pll logic before driving the internal gates. note that this signal cannot be used in the same quadrant where the pll signal is used (pllclk_out). pllclk_out out from pll to internal gates this signal can drive the internal gates after going through the pll. for this to work, onn_offchip must be tied to gnd. pllpad_out out to off-chip this outgoing signal is used off-chip. for this to work, onn_offchip signal must be tied to vcc. lock_detect active high lock detection signal note: for simulation purposes, this signal gets asserted after 10 clock cycles. however, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the reset signal. preliminary 4 !# eclipse-ii features a variety of distinct i/o pins to maximize performanc e, functionality, and flexibility with bi-directional i/ o pins and input-only pins. all input and i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply wi th the specific i/o standard selected. for single ended i/o standards, vccio specifies the in put tolerance and the output driv e. for voltage referenced i/o standards (e.g sstl), the voltage supplied to the inref pins in each bank specifies the input switch point. for example, the v ccio pins must be tied to a 3.3 v supply to provide 3.3 v compliance. eclipse-ii can also support the lvds and lvpe cl i/o standards with the use of external resistors ( see < 3 ). as designs become more complex and requirements more stringent, several application-specific i/o standa rds have emerged for specific applications. i/o standards for processors, memories, and a variety of bus ap plications have become commonplace and a requirement for many systems. in addition, i/o ti ming has become a greater issue with specific requirements for setup, hold, cloc k to out, and switching times. eclipse-ii has addressed these new system requirements and now includes a completely new i/o cell which consists of programmable i/os as well as a ne w cell structure consisting of th ree registers?input, output, and oe. eclipse-ii offers banks of progra mmable i/os that address many of the bus standards that are popular today. as shown in = each bi-directional i/o pin is associated with an i/o cell which features an input register, an input buffer, an output register , a three-state output buffer, an output enable register, and 2 tw o-to-one output multiplexers. ?!", & &/ & ! " -"7 ! ' 7 '' " lvttl n/a 3.3 v general purpose lvcmos25 n/a 2.5 v general purpose lvcmos18 n/a 1.8 v general purpose pci n/a 3.3 v pci bus applications gtl+ 1 n/a backplane sstl3 1.5 3.3 v sdram sstl2 1.25 2.5 v sdram preliminary ( )* the bi-directional i/o pin options can be prog rammed for input, outpu t, or bi-directional operation. as shown in = , each bi-directional i/o pin is as sociated with an i/o cell which features an input register, an input buffer, an outp ut register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. the select lines of the two-to-one multiplexers are static and must be connected to either vcc or gnd. for input functions, i/o pins can provide combinatorial, regi stered data, or both options simultaneously to the logic array. for combinatoria l input operation, data is routed from i/o pins through the input buffer to the a rray logic. for registered input operation, i/o pins drive the d input of input cell registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. th e comparator and multiplexor in th e input path allows for native support of i/o standards with reference points offset from traditional ground. for output functions, i/o pins can receive combinatorial or register ed data from the logic array. for combinatorial output operation, data is rout ed from the logic array through a multiplexer to the i/o pin. for registered output operation, the array logic drives the d input of the output cell register which in turn drives the i/o pin throug h a multiplexer. the mult iplexer allows either a combinatorial or a registered signal to be driven to the i/o pin. the addition of an output register will also decrease the tco. since the output register does not need to drive the routing the length of the output path is also reduced. the three-state output buffer cont rols the flow of data from th e array logic to the i/o pin and allows the i/o pin to act as an input and/or outp ut. the buffer's output enab le can be individually controlled by the logic cell array or any pin (throu gh the regular routing resources), or it can be bank-controlled through one of the global networks . the signal can also be either combinatorial e r q d r q d e r q d + - pad output enable register output register input register preliminary 0 or registered. this is identical to that of the flow for the output cell. for combinatorial control operation data is routed from the logic array thro ugh a multiplexer to the three-state control. the ioctrl pins can directly drive the oe and clk signals for all i/o cells within the same bank. for registered control operation, the array logic drives the d input of th e oe cell register which in turn drives the three-state control through a multiplexer. the multip lexer allows either a combinatorial or a registered signal to be driven to the three-state control. when i/o pins are unused, the oe controls can be permanently disabled, allowing the output cell register to be used for register ed feedback into the logic array. i/o cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the gl obal networks, or from two ioctrl input pins per bank of i/o's. the clk and reset signals sh are common lines, whil e the clock enables for each register can be independently controlled. i/o interface support is programmable on a per bank basis. the two larger eclipse-ii devices co ntain eight i/o banks.the two smaller eclipse-ii devices contain two i/o banks per device. 3 illustrates the i/o bank configurations. each i/o bank is independent of other i/o banks and each i/o bank has its own vccio and inref supply inputs. a mixture of different i/o standards can be used on the device; however, there is a limitation as to which i/o standard s can be supported within a given bank. only standards that share a common vccio and inref can be shared within the same bank (e.g. pci and lvttl). + " )*, & each i/o has programmable slew rate capability?the slew rate can be eith er fast or slow. the slower rate can be used to reduc e the switching times of each i/o. embedded ram blocks pll pll fabric embeded computational units embedded ram blocks pll pll vccio 0 inref 0 vccio 1 inref 1 vccio 2 inref 2 vccio 3 inref 3 inref 4 vccio 4 inref 5 vccio 5 inref 6 vccio 6 inref 7 vccio 7 preliminary 6 2$ /&" a programmable weak pull-down resistor is av ailable on each i/o. the i/o weak pull-down eliminates the need for external pull down resist ors for used i/os. the sp ec for pull-down current is maximum of 150 a under worst case condition. - ' )*.' /, # $% &$ , # $ there are a maximum of eight global clock networks in each eclipse-ii device. global clocks can drive logic cells and i/o registers, ecus, and ram blocks in the device. a ll global clocks have access to a quad net (l ocal clock network) connection with a programmable connection to the logic cell?s register clock input. i/o output logic pa d preliminary ; 0 ! 1 1/% % &$ there are five quad-net local clock networks in each quadrant for a total of 20 in a device. each quad-net is local to a quadrant. before driving the co lumns clock buffers, the quad-net is driven by the output of a mux which selects betw een the gclk input and an internally generated clock source (see ). 0 2 2 1 quad net gclk pin global clock net t pgck t bgck internally generated clock, or clock from general routing network global clock (gclk) input global clock network ff global clock buffer preliminary 5 # $ there is one dedicated clock in the two larger devices of the eclipse-ii family (ql8325 and ql8250). this clock connects to th e clock input of the logiccell and i/o registers, and ram blocks through a hardwired conn ection and is multiplexed with the programmable clock input. the dedicated clock provides a fast global network with low skew. us ers have the ability to select either the dedicated clock or the programmable clock ( 0 ). # # 3/ 1, note: &1 & &' & 1 @/= ' .9 / &* >? !#" " / each bank of i/os has two input-only pins that can be programmed to drive the rst, clk, and en inputs of i/os in that bank. these input-only pins also serve as high drive inputs to a quadrant. these buffers can be driven by the internal logic both as an i/o control or high drive. the performance of these drives is presented in < 8 . " eclipse-ii devices are delivered with six types of routing resources as fo llows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distribut ed networks, and default wires. short wires span the length of one logic cell , always in the vertical direction. dual wires run horizontally and span the length of two logic ce lls. short and dual wires are predominantly used for local connections. default wires supply vcc and gnd (logic ?1? and logic ?0?) to each column of logic cells. quad wires have passive link interconnect elements every fourth logic cell. as a result, these wires are typically used to implement intermed iate length or me dium fan-out nets. a!"% & * !9 8 '#$ " " <<.05 #.0?57 + i/o (far) 1.00 ns 1.14 ns i/o (near) 0.63 ns 0.78 ns skew 0.37 ns 0.36 ns programmable clock or general routing dedicated clock clk preliminary 9 express lines run the length of the programmable logic uninterrupt ed. each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. the re sistance will also be lower because the express wires don't require the use of "p ass" links. express wires provid e higher performance for long routes or high fan-out nets. distributed networks are described in the cl ock/control section. these wires span the programmable logic and are driven by "column cloc k" buffers. all clock network pin buffers (both dedicated and global) are hard wired to in dividual sets of co lumn clock buffers. , &/!" )! * the eclipse-ii family of devices features a global power- on reset. this reset is hardwired to all registers and resets them to logic ?0? upon powe r-up of the device. in quicklogic devices, the aynchronous reset input to flip-flops has priority over the se t input; therefore, the global por will reset all flip-flops during powe r-up. if you want to set the flip-fl ops to logic ?1?, you must assert the ?set? signal after the global por signal has been deasserted. '/*, && power consumption of the two smaller eclipse-ii devices can be reduced significantly by de- activating the charge pumps insi de the architecture. by applying 3.3 v to the vpump pin, the internal charge pump is de-activated?this effe ctively reduces the dynamic power consumption of the device. users who have a 3.3 v supply availabl e in their system should take advantage of this low power feature by tying the vpump pin to 3.3 v. otherwise, if a 3.3 v supply is not available, this pin should be tied to ground. vcc power-on reset q xxxxxxx 0 preliminary = @" < ,')@< ,* "- " 45!0 microprocessors and application specific integrated circuits (asics) pose many design challenges, one problem being the accessibility of test points. jtag formed in response to this challenge, resulting in ieee stan dard 1149.1, the standard test ac cess port and boundary scan architecture. the jtag boundary scan test methodology allo ws complete observation and control of the boundary pins of a jtag-compa tible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run three required tests along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boun dary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (v ia the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan regist er to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register preliminary 3 bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data pa sses through the bypass register. th e bypass instruction allows users to test a device without passing through othe r devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device. @< ,:'' bsdl-boundary scan description language machine-readable data for te st equipment to generate testing vectors and software bsdl files available for all device/ package combinations from quicklogic extensive industry support av ailable and atvg (automatic test vector generation) +- there are two security links: one to disable readin g logic from the array, an d the second to disable jtag access to the devi ce. programming these optional links co mpletely disables access to the device from the outside world and provides an extr a level of design security not possible in sram- based fpgas. the option to program these fu ses is selectable via quickworks in the tools/options/device programming window in spde. +- the flexibility link enables power-up loading of the embedded ram blocks. if the link is programmed, the power up loading state machine is activated during power-up of the device. the state machine communicates with an extern al eprom via the jtag pins to download memory contents into the on-chi p ram. if the link is not prog rammed, power-up loading is not enabled and the jtag pins function as they norma lly would. the option to program this bit is selectable via quickworks in the tools/options/device prog ramming window in spde. for more information on power-up loading re fer to quicklogic application note 55. preliminary 8 '- " ## the dc specifications are provided in < 4 through < 0 . b/ < & 7 7 v cc voltage -0.5 v to 2.0 v dc input current 20 ma v ccio voltage -0.5 v to 4.0 v esd pad protection 2000 v inref voltage 0.5 v to v ccio leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to v ccio + 0.5 v laminate package (bga) storage temperature -55 c to + 125 c latch-up immunity 100 ma " & < & + + " # (" " " " v cc supply voltage 1.71 1.98 1.71 1.98 1.71 1.98 v v ccio i/o input tolerance voltage 1.71 3.60 1.71 3.60 1.71 3.60 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -7 speed grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a -8 speed grade 0.42 1.27 0.43 1.19 0.46 1.16 n/a preliminary 04 #%%' + #" " " (" i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd - 10 a c i i/o input capacitance a % & & % & - - 8 pf c clock clock input capacitance - - 8 pf i os output short circuit current b b. only one output at a time. du ration should not exceed 30 seconds. v o = gnd v o = v cc -15 40 -180 210 ma ma i ded d.c. supply current on v ded - - - ma i ref d.c. supply current on inref - -10 10 a i pd current on programmable pull-down v ccio = 3.6 v v ccio = 2.5 v v ccio = 1.8 v - 150 a 0%' 7''a47 7''a6?67 ql8025 - - ql8050 - - ql8150 - - ql8250 a a. for -7/-8 commercial grade devices only. maximum i cc is 3 ma for all industrial grade devices and 5 ma for all military devices. 2 ma - ql8325 a 2 ma - preliminary 0 2#%& &"9$ a. the data provided in < 3 and < 8 are jedec and pci specifications. quicklogic devices either meet or exceed these requirements. for data specific to quicklogic i/os, see preceding < 04 through < 0; , = through 8 , and 06 through 09 . note: /%9: &"% <9& 'c '1 ='& & $& c db0c % 7 7 7 ! 7 ! ! ! 7 % 7 b 7 % 7 b 7 % 7 b 7 b 7 % lvttl n/a n/a -0.3 0.8 2.2 v ccio + 0.3 0.4 2.4 2.0 -2.0 lvcmos2 n/a n/a -0.3 0.7 1.7 v ccio + 0.3 0.7 1.7 2.0 -2.0 lvcmos18 n/a n/a -0.3 0.63 1.2 v ccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x v ccio 0.5 x v ccio v ccio + 0.5 0.1 x v ccio 0.9 x v ccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 v ccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 1.10 1.90 8 -8 preliminary 00 ## the ac specifications (at v cc = 1.8 v, ta = 25 c, worst case corner, speed grade = -7 (k = 1.16)) are provided from < 5 to < 0; . logic cell diagrams and waveforms are provided from 5 to 0= . $ logic cell 79 % + 7 # " t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output - 0.257 ns t su setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.22 ns - t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t co clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. - 0.255 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns - t cwlo clock low time: required minimum time that the clock stays low 0.46 ns - t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) - 0.18 ns t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.09 ns t sw set width: time that the set signal must remain high/low 0.3 ns - t rw reset width: time that the reset signal must remain high/low 0.3 ns - preliminary 06 & 6 ( 5,7 .86 set d clk reset q set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw preliminary 0; + 5,72 ,#.86 note: 6'&& 99= @%: & 4@%: 11$ e f & ' 9 9 > % # # $ # $-" , logic cells (internal) clock signal generated internally 1.51 ns (max) - clock pad clock signal generated externally 2.06 ns (max) 1.73 ns 5 @ % # # $ " 7 " t pgck global clock pin delay to quad net - 1.34 ns t bgck global clock tree delay (quad net to flip-flop) - 0.56 ns clk d q t su t hl t co preliminary 05 - 0 2 2 1 !""# quad net wa wd we wclk re rclk ra rd ram module [9:0] [17:0] [9:0] [17:0] as yncr d preliminary 09 !" 23, 1,. 5, ? + 7 # +" " 2 <" " t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.675 ns - t hwa wa hold time to wclk: time the write address must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.654 ns - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.623 ns - t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 4.38 ns t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd preliminary 0= !" 23, 1, ,#!3, 1, #5, a + 7 # +" " <" " t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.686 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.243 ns - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 ns - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 4.38 ns # +" " <" r pdrd ra to rd: time between when the read address is input and when the data is output - 2.06 ns t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd preliminary 03 )* + - pad output register preliminary 08 , b&< % + ) "' # !" +* 7 " t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 2.50 ns - t ihl input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge - 0 ns t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge - 1.08 ns pad t isu t sid + - q e d r preliminary 64 $ , 5, t irst input register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low) - 0.99 ns t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge 0.37 ns - t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge 0 ns - b&< % + ) "' # !" +* 7 " r clk d q tisu tih l tico tiesu tieh tirst e preliminary 6 & * , & &# + 7 " "' + < "' + + ( " t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.34 ns t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.42 ns t sid (lvcmos18) lvcmos18 input delay: low voltage cmos for 1.8 v applications - - t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.68 ns t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.55 ns t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.61 ns pad output register preliminary 60 ( * 5, ",< gc %%" h00c= h 7 % & & & rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns 0",< gc %%" h 7c= h 7 % & & & rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns 2",< gc %%" h?c= h 7 % & & & rising edge - - falling edge - - l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz preliminary 66 $ < # thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power di ssipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: f& & ) i /j -7bk% ' &1 $ i/ 1 < 05 = & / /j & p max = (150o c - t amax )/ ja 7 ' %' $ ' " ja )c# 2*d - & ) * jc )c# 2* "#" $ <+' 4 4?5 0 484 pbga 28.0 26.0 25.0 23.0 9.0 280 lf-pbga 18.5 17.0 15.5 14.0 7.0 208 pqfp 26.0 24.5 23.0 22.0 11.0 preliminary 6; e"e ,' + 9 8:2 39 - 5 8:* ,5 voltage factor vs. supply voltage 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 supply voltage (v) kv temperature factor vs. operating temperature 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 junction temperature c kt preliminary 65 & ?!' " >"+ the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins note: & & &= 1 / &* l>b &/'>"" '/ 2;, , the following requirements must be met when powering up a device (refer to 64 ): when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. deviation from this recommendation can cause perman ent damage to the device. v ccio must lead v cc when ramping the device. the power supply must be greater th an or equal to 400 s to reach v cc . ramping to v cc /v ccio before reaching 400 s can cause the device to behave improperly. voltage v ccio v cc (v ccio -v cc ) max 400 us v cc preliminary 69 " ' " )*,/ 1 8, ', >i /@&# & " " " ' " tdi/rsi test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to v cc if unused trstb/rro active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag tdo/rco test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g) preliminary 6= 5# &# & " " " ' " gclk global clock network driver low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. i/o(a) input/output pin the i/o pin is a bi-directional pin, configurable to either an input- only, output-only, or bi-directional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. v cc power supply pin connect to 1.8 v supply v ccio (a) input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the a inside the parenthesis means that v ccio is located in bank a. every i/o pin in bank a will be tolerant of v ccio input signals and will output v ccio level signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. gnd ground pin connect to ground pllin pll clock input clock input for pll dedclk dedicated clock pin low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g. ram, flip flops). gndpll ground pin for pll connect to gnd inref(a) differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in < for the appropriate standard. the a inside the parenthesis means that inref is located in bank a. this pin should be tied to gnd if not needed. pllout pll output pin dedicated pll output pin; otherwise, may be left unconnected ioctrl(a) highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. there is an internal pulldown resistor to ground on this pin. this pin should be tied to ground if it is not used. for backwards compatibility with eclipse, it can be tied to vcc or ground. if tied to vcc, it will draw no more than 20 a per ioctrl pin due to the pulldown resistor. ) -0* preliminary 63 vpump charge pump disable this pin disables the internal charge pump for lower static power operation. to disable the charge pump, connect vpump to 3.3 v. if the disable charge pump feature is not used, connect vpump to ground. for backwards compatibility with eclipse and eclipseplus devices, connect vpump to ground. vded voltage tolerance for clocks, jtag, and ioctrl/voltage drive for pllout and jtag pins this pin specifies the input voltage tolerance for clk, jtag, and ioctrl dedicated input pins, as well as the output voltage drive for pllout and jtag pins. if the plls are used, vded must be the same as v cc pll. for backwards compatibility with eclipse and eclipseplus devices, connect vded to 2.5 v. vccpll power supply pin for pll connect to 2.5 v supply or 3.3 v supply. for backwards compatibility with eclipse and eclipseplus devices, connect to 2.5 v. 5# &# & " " " ' " ) 0-0* preliminary 68 "(" "<" " - ' / all unused, general purpose i/o pins can be tied to v cc , gnd, or hiz (high impedance) internally using the configuration editor. th is option is given in the botto m-right corner of the placement window. to use the placement editor, choose constraint > fix placement in the option pull- down menu of spde. the rest of the pins should be terminated at the board level in the manner presented in < 03 . 0431" ?< &3&& & & " % "<" " pllout preliminary ;4 preliminary ; 0431" < a b?. & 1 " " 1 " " 1 " " 1 " " 1 " " 99<, )0- ;6 ")4- 35 ")#- 0= %9:)7-=99*)0- 98 ")@- 0 c %%99 )0- ;; c %%" )4- 39 c %% 03 %9:)>- =4 *< )@- 6 @*# ;5 ")4- 3= ")#- 08 c = ")@- ; @*# ;9 c %% 33 ")#- 64 %9:)5- =0 ")@- 5 ")/- ;= ")4- 38 c %% 6 c %% =6 ")@- 9 ")/- ;3 ")4- 84 ")#- 60 %9:)?- =; ")c- = ")/- ;8 @*# 8 ")#- 66 , =5 c %% 3 c %%" )/- 54 #" 80 ")#- 6; ") - =9 ")@- 8 ")/- 5 99"3 )- 86 *< )#- 65 ") - == c %%" )@- 4 ")/- 50 @*#99) - 8; ")#- 69 ") - =3 @*# ")/- 56 @*# 85 ")#- 6= @*# =8 ")@- 0 c %% 5; c %%99 ) - 89 ")#- 63 c %%" ) - 34 ")@- 6 *< )/- 55 99<, ) - 8= ")#- 68 ") - 3 ")@- ; ")/- 59 c %% 83 c %%" )#- ;4 ") - 30 c %% 5 ")/- 5= ")%- 88 ")#- ; ") - 36 %: 9 ")/- 53 @*# 44 ")#- ;0 ") - 3; c %% = ")/- 58 ")%- 4 c ;6 ") - 35 ")8- 3 ")/- 94 c %%" )%- 40 99"3 )b- ;; ") - 39 ")8- 8 c %%" )/- 9 ")%- 46 @*# ;5 *< ) - 3= ")8- 04 ")/- 90 ")%- 4; @*#99)- ;9 c %% 33 @*# 0 @*# 96 ")%- 45 99<, )- ;= ") - 38 c %%" )8- 00 ")/- 9; ")%- 49 c %%99 )- ;3 ") - 84 ")8- 06 # 95 ")%- 4= ")- ;8 ") - 8 ")8- 0; %9:)b- 99 ")%- 43 @*# 54 c %%" ) - 80 ")8- 05 %9:)- 9= ")%- 48 ")- 5 ") - 86 ")8- 09 c %% 93 *< )%- 4 ")- 50 ") - 8; *)8- 0= %9:) -=99*) - 98 ")%- c %%" )- 56 @*# 85 c %% 03 %9:)0-=99*)- =4 ")%- 0 ")- 5; ") - 89 ")8- 08 c = ")%- 6 c %% 55 99"3 )0- 8= ")8- 64 %9:)2-= ##%9:=99*)b- =0 c %%" )%- ; ")- 59 @*#99)b- 83 ")8- 6 ")4- =6 ")%- 5 ")- 5= @*# 88 ")8- 60 ")4- =; ")%- 9 ")- 53 c %%99 )b- 044 ")8- 66 @*# =5 @*# = ")- 58 99<, )b- 04 ")8- 6; c %%" )4- =9 c %% 3 *< )- 94 @*# 040 ")8- 65 ")4- == ")%- 8 ")- 9 ")@- 046 c %%" )8- 69 ")4- =3 <, 4 04 ")- 90 c %%" )@- 04; @*# 6= ")4- =8 c %% 0 ")- 96 ")@- 045 ")8- 63 ")4- 34 ")#- 00 c %%" )- 9; ")@- 049 99"3 ) - 68 ")4- 3 ")#- 06 @*# 95 c %% 04= @*# ;4 *< )4- 30 ")#- 0; ")- 99 ")@- 043 @*#99)0- ; ")4- 36 @*# 05 ")- 9= ")@- ;0 ")4- 3; c %%" )#- 09 ")- 93 ")@- preliminary ;0 034:, " <' : eclipse-ii ql8325-7pt280c pin a1 corner preliminary ;6 034:, " < 0b ?b4@/& :, " " :, " " :, " " :, " " :, " " :, " " 99"3 m0n #4 %9:m7n !99*m0n 8 "% <9m#n e9 !"m%n ; !"m8n (6 !"m4n 0 @*#99mbn # c %%" mn *< m@n e= !"m#n 5 @*# (; "% <9m4n 6 !"m n #0 !"mn 0 "% <9m@n e3 !"m%n 9 @*# (5 c %%" m4n ; !"m n #6 !"mn 6 !"m@n e8 <, 4 = c %% (9 !"m4n 5 !"m n #; !"mn ; !"m@n !"m8n 3 c %% (= #" 9 "% <9m n #5 c %%" mn 5 @*# 0 !"m8n 8 @*# (3 99<, m n = !"m n #9 !"mn 5 c %% 6 c %%" m8n 4 @*# (8 !"m4n 3 !"m n #= !"mn 9 "% <9m#n ; !"m8n c %% 7 99"3 m n 8 !"m n #3 !"mn = !"m#n 5 c %% 0 c %% 70 @*#99m0n 4 %9:m5n #8 !"mn 3 !"m#n 5 @*# 6 c %% 76 @*# !"mn !"m@n 8 !"m#n 9 !"m%n ; c 7; !"m/n 0 !"mn 0 !"m@n , !"m@n = c %%" m%n 5 @*# 75 !"m/n 6 !"mn 6 !"m n ,0 !"m@n 3 !"m%n 9 !"m%n 79 "% <9m/n ; "% <9mn ; !"m n ,6 "% <9m@n 8 !"m%n = c %%" m%n 7= !"m/n 5 !"mn 5 !"m n ,; !"m@n !"m8n 3 !"m%n 73 !"m/n 9 !"mn 9 !"m n ,5 c %% 0 !"m8n 8 !"m%n 78 !"m/n = !"mn = !"m n ,5 c %% 6 !"m8n < !"m8n 74 %9:mn 3 99<, mn 3 !"m n ,9 !"m#n ; !"m8n <0 !"m8n 7 %9:m2n ##%9:!99*mbn 8 @*# 8 %9:m?n ,= !"m#n 5 c %% <6 !"m/n 70 !"m4n : 99<, mbn 4 !"mn ,3 !"m#n 5 c %% <; !"m/n 76 !"m4n :0 @*# !"mn ,8 !"m#n 9 *< m%n <5 !"m/n 7; *< m4n :6 !"m n 0 !"mn !"m@n = !"m%n <9 "% <9m/n 75 !"m4n :; !"m n 6 *< mn 0 !"m@n 3 !"m%n <= !"m/n 79 !"m4n :5 !"m n ; !"mn 6 !"m@n 8 !"m%n <3 !"m/n 7= !"m4n :9 *< m n 5 !"mn ; !"m@n % "% <9m8n <8 !"m/n 73 @*#99m n := !"m n 9 !"m#n 5 c %% %0 !"m8n <4 !"m/n 78 @*# :3 !"m n = !"m#n 5 c %% %6 !"m8n < %9:m0n !99*mn 2 @*# :8 , 3 !"m#n 9 c %% %; !"m8n <0 !"m4n 20 99<, m0n :4 %9:m>n 8 !"m#n = !"m#n %5 c %% <6 !"m4n 26 !"m/n : !"mn !"m@n 3 !"m#n %5 c %% <; !"m4n 2; !"m/n :0 !"mn 0 !"m@n 8 !"m#n %9 !"m%n <5 !"m4n 25 !"m/n :6 "% <9mn 6 c %%" m@n @ !"m@n %= !"m%n <9 !"m4n 29 !"m/n :; !"mn ; !"m n @0 !"m@n %3 "% <9m%n <= c %%99 m n 2= !"m/n :5 !"mn 5 @*# @6 c %%" m@n %8 "% <9m%n <3 !"m4n 23 !"m/n :9 !"mn 9 c %% @; !"m@n !"m8n <8 !"m4n 28 # := c %%99 mn = c %% @5 @*# 0 !"m8n ( !"m/n 24 %9:m n !99*m n :3 @*#99mn 3 c @5 c %% 6 "% <9m8n (0 !"m/n 2 !"m4n :8 99"3 mbn 8 c %% @9 !"m%n ; *< m8n (6 c %%99 m0n 20 !"m4n # !"m n 4 @*# @= c %%" m#n 5 c %% (; !"m/n 26 !"m4n #0 c %%99 mbn @*# @3 !"m#n 5 @*# (5 c %%" m/n 2; "% <9m4n #6 !"m n 0 c %% @8 !"m#n 9 !"m%n (9 *< m/n 25 !"m4n #; !"m n 6 c %% e c %% = !"m%n (= !"m/n 29 !"m4n #5 c %%" m n ; @*# e0 %: 3 !"m%n (3 !"m/n 2= !"m4n #9 "% <9m n 5 c e6 !"m@n 8 !"m%n (8 c %%" m/n 23 !"m4n #= !"m n 9 !"m#n e; !"m@n !"m8n (4 %9:mbn 28 99"3 mn #3 !"m n = c %%" m#n e5 @*# 0 !"m8n ( c %%" m4n #8 c %%" m n 3 *< m#n e5 @*# 6 c %%" m8n (0 !"m4n preliminary ;; ;3;:, " <' : eclipse-ii ql8325-7ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 ab aa pin a1 corner pin a1 preliminary ;5 ;3;:, " < 02?24@/& :, " " :, " " :, " " :, " " :, " " :, " " !"m/n # !"m/n "% <9m/n , !"m/n @ !"m/n %9:m2n ##%9:!99*mbn 0 99<, m0n #0 !"m/n 0 !"m/n ,0 !"m/n @0 !"m/n 0 %9:mbn 6 !"m/n #6 c %%99 m0n 6 !"m/n ,6 !"m/n @6 !"m/n 6 %9:m n!99*m n ; !"m/n #; 99"3 m n ; !"m/n ,; !"m/n @; !"m/n ; !"m/n 5 !"m/n #5 !"m/n 5 !"m/n ,5 !"m/n @5 !"m/n 5 !"m/n 9 !"m8n #9 !"m8n 9 !"m8n ,9 !"m/n @9 !"m/n 9 !"m/n = !"m8n #= !"m8n = *!% ,= @*# @= !"m/n = @*# 3 "% <9m8n #3 !"m8n 3 !"m8n ,3 !"m8n @3 c %% 3 @*# 8 !"m8n #8 "% <9m8n 8 !"m8n ,8 !"m8n @8 @*# 8 @*# 4 *!% #4 !"m8n 4 !"m8n ,4 !"m8n @4 c %% 4 @*# *!% # !"m8n c %% , !"m@n @ c %% @*# 0 %: #0 !"m8n 0 !"m@n ,0 @*# @0 @*# 0 @*# 6 !"m@n #6 !"m@n 6 !"m@n ,6 !"m@n @6 c %% 6 @*# ; !"m@n #; !"m@n ; !"m@n ,; !"m@n @; @*# ; c %% 5 !"m@n #5 !"m@n 5 "% <9m@n ,5 !"m@n @5 c %% 5 c %% 9 !"m@n #9 !"m@n 9 !"m@n ,9 c @9 !"m n 9 %9:m>n = !"m@n #= !"m@n = *< m@n ,= c %%" m n @= c %%" m n = c %%" m n 3 !"m@n #3 !"m@n 3 !"m@n ,3 !"m n @3 !"m n 3 !"m n 8 !"m n #8 !"m n 8 !"m n ,8 !"m n @8 !"m n 8 %9:m?n 04 @*# #04 @*#99mbn 04 !"m n ,04 !"m n @04 !"m n 04 !"m n 0 99"3 m0n #0 !"m n 0 !"m n ,0 *< m n @0 !"m n 0 !"m n 00 !"m n #00 !"m n 00 !"m n ,00 !"m n @00 !"m n 00 !"m n : !"m/n !"m/n !"m/n !"m/n e # !"m4n :0 @*# 0 !"m/n 0 *< m/n 0 !"m/n e0 !"m/n 0 !"m4n :6 @*#99m0n 6 !"m/n 6 !"m/n 6 !"m/n e6 !"m/n 6 !"m4n :; @*# ; !"m/n ; !"m/n ; !"m/n e; !"m/n ; %9:m0n!99*mn :5 !"m/n 5 !"m/n 5 !"m/n 5 "% <9m/n e5 !"m/n 5 !"m4n :9 !"m8n 9 !"m8n 9 c %%" m/n 9 c %%" m/n e9 c %%" m/n 9 c %%" m4n := !"m8n = !"m8n = c %%" m8n = !"m8n e= !"m/n = %9:mn :3 *< m8n 3 !"m8n 3 !"m8n 3 @*# e3 c %% 3 c %% :8 !"m8n 8 !"m8n 8 c %%" m8n 8 c %% e8 c %% 8 c %% :4 !"m8n 4 !"m8n 4 !"m8n 4 c %% e4 @*# 4 @*# : !"m8n !"m8n c %%" m8n c e @*# @*# :0 *!% 0 !"m@n 0 c %%" m@n 0 @*# e0 @*# 0 @*# :6 *!% 6 !"m@n 6 !"m@n 6 c %% e6 @*# 6 @*# :; *!% ; !"m@n ; c %%" m@n ; c %% e; c %% ; @*# :5 !"m@n 5 "% <9m@n 5 *!% 5 @*# e5 c %% 5 @*# :9 !"m@n 9 !"m@n 9 c %%" m@n 9 !"m n e9 !"m n 9 @*# := !"m@n = !"m@n = *!% = !"m n e= !"m n = !"mn :3 !"m@n 3 !"m n 3 !"m n 3 !"m n e3 !"m n 3 !"mn :8 99<, mbn 8 c %%99 mbn 8 !"m n 8 !"m n e8 !"m n 8 !"mn :04 !"m n 04 !"m n 04 "% <9m n 04 !"m n e04 !"m n 04 %9:m5n :0 !"m n 0 !"m n 0 !"m n 0 !"m n e0 !"m n 0 %9:m7n!99*m0n :00 !"m n 00 !"m n 00 "% <9m n 00 !"m n e00 !"m n 00 , ) -0* preliminary ;9 % !"m4n 9 !"mn <8 *!% 70 !"m4n 2= !"m#n 4 !"m%n %0 !"m4n = !"mn <4 <, 4 76 !"m4n 23 !"mn !"m%n %6 !"m4n 3 !"mn < @*# 7; !"m4n 28 !"mn 0 !"m#n %; !"m4n 8 !"mn <0 *!% 75 !"m4n 204 !"mn 6 !"m#n %5 !"m4n 04 !"mn <6 !"m#n 79 !"m%n 20 !"mn ; !"m#n %9 !"m4n 0 !"mn <; *!% 7= !"m%n 200 !"mn 5 !"m#n %= !"m4n 00 !"mn <5 !"m#n 73 !"m%n f !"m4n 9 !"m#n %3 c %% !"m4n <9 @*# 78 *!% f0 !"m4n = !"m#n %8 c %% 0 *< m4n <= !"mn 74 !"m%n f6 c %%99 m n 3 !"m#n %4 @*# 6 !"m4n <3 !"mn 7 !"m%n f; !"m%n 8 !"mn % @*# ; !"m4n <8 !"mn 70 c %% f5 !"m%n 04 @*#99mn %0 @*# 5 !"m4n <04 !"mn 76 *!% f9 !"m%n 0 !"mn %6 @*# 9 !"m4n <0 "% <9mn 7; !"m#n f= !"m%n 00 !"mn %; c %% = !"m4n <00 !"mn 75 !"m#n f3 "% <9m%n : !"m4n %5 c %% 3 @*# ( "% <9m4n 79 *< m#n f8 !"m%n :0 @*#99m n %9 !"mn 8 c %% (0 !"m4n 7= !"m#n f4 !"m%n :6 99<, m n %= c %%" mn 4 c %% (6 "% <9m4n 73 !"mn f !"m#n :; !"m4n %3 !"mn @*# (; !"m4n 78 !"mn f0 !"m#n :5 !"m4n %8 !"mn 0 c (5 !"m4n 704 !"mn f6 !"m#n :9 !"m%n %04 !"mn 6 c %% (9 !"m%n 70 !"mn f; !"m#n := !"m%n %0 !"mn ; c %% (= c %%" m%n 700 !"mn f5 "% <9m#n :3 "% <9m%n %00 !"mn 5 @*# (3 *!% 2 !"m4n f9 !"m#n :8 !"m%n !"m4n 9 !"m#n (8 c %%" m%n 20 !"m4n f= !"m#n :4 !"m%n 0 !"m4n = c %%" mn (4 !"m%n 26 !"m4n f3 !"mn : !"m%n 6 !"m4n 3 !"mn ( c %%" m%n 2; !"m4n f8 99"3 mbn :0 !"m#n ; !"m4n 8 !"mn (0 c %%" m#n 25 !"m4n f04 99<, mn :6 !"m#n 5 !"m4n 04 !"mn (6 !"m#n 29 !"m%n f0 !"mn :; !"m#n 9 c %%" m4n 0 !"mn (; c %%" m#n 2= *!% f00 !"mn :5 !"m#n = !"m4n 00 !"mn (5 *!% 23 !"m%n #" :9 "% <9m#n 3 c %% < !"m4n (9 c %%" m#n 28 !"m%n 0 99"3 mn := !"m#n 8 @*# <0 !"m4n (= c %%" mn 24 !"m%n 6 @*# :3 !"m#n 4 c %% <6 !"m4n (3 !"mn 2 !"m%n ; !"m4n :8 !"mn @*# <; !"m4n (8 !"mn 20 !"m#n 5 !"m%n :04 @*# 0 c %% <5 !"m4n (04 "% <9mn 26 !"m#n 9 !"m%n :0 c %%99 mn 6 c %% <9 c %%" m4n (0 !"mn 2; !"m#n = !"m%n :00 !"mn ; @*# <= @*# (00 *< mn 25 !"m#n 3 *< m%n 5 c %% <3 !"m%n 7 !"m4n 29 *!% 8 !"m%n 02?24@/& )% &&- :, " " :, " " :, " " :, " " :, " " :, " " ) 0-0* preliminary ;= $ " "- " the eclipse-ii product family packaging in formation is presented in < 60 . note: & 1 & ' && 0 & " & "- " 13605 13054 1354 13454 13405 " " " " " b?. b7b b?. b7b bbc. b7b bbc. b7b bbc. b7b #1& & a. pqfp = plastic quad flat pack; bg a= ball grid array; vqfp = very thin quad flat pack; csbga = chip scale ball grid array; fbga = fine pitch ball grid array !" "- " ?b 4@/ b?b ?b 4@/ b?b b?. b7b b?. b7b b?. b7b 2?24@/ b 2?24@/ b a> %,4@/ b?b a> %,4@/ b?b a> %,4@/ b?b ql 8050 -7 pq208 c operating range: c = commercial i = industrial m = military package lead count: pv100 = 100-pin vqfp pq208 = 208-pin pqfp pt196 = 196-ball chip scale bga (0.8 mm) pt280 = 280-ball fpbga (0.8 mm) ps484 = 484-ball fpbga (1.0 mm) 8150, part number: 8050, 8250, 8325 quicklogic device speed grade: 7 faster 8 fastest 8025, preliminary ;3 #" "- " telephone: 408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/ " + 00<$ &8 " #" a preliminary august 2002 brian faith, judd heape, andreea rotaru rev a december 2002 brian faith, andreea rotaru rev b january 2003 brian faith, andreea rotaru preliminary ;8 #'+ "< $ "- " copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this document and the accomp anying software programs is protected by copyright. all righ ts are reserved by quicklog ic corporation. quicklogic corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. copying, duplica ting, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic and the quicklogic logo, pa sic, vialink, deskfab, and quickworks are registered trademarks of quicklogic corporation; ecli pse, quickfc, quickdsp, quickdr, quicksd, quicktools, quickcore, quickpro, spde, webasic, and webesp are trademarks of quicklogic corporation. |
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